1. Field of the Invention
The invention relates in general to the fabrication of a semiconductor memory for an integrated circuit (IC) device. In particular, the invention relates to a process for fabricating a self-aligned contact for a memory IC device, having an improved performance and fabrication yield rate.
2. Description of the Related Art
Among semiconductor IC fabrication processes for memory devices, aknown technique using what is known as a "self-aligned contact" is widely employed to reduce the surface area of the layout of the device memory cell units. Smaller memory cell units may be directly translated into higher memory density for the device fabricated. FIGS. 1A-1C of the accompanying drawings are cross-sectional views depicting a self-aligned contact at successive steps of fabrication by a conventional process.
As is shown in the drawing, a memory cell is fabricated in a semiconductor substrate 10, which can be a P-type silicon substrate or a P-well region in a silicon substrate. A gate dielectric layer 11 for the memory cell unit may be a silicon oxide layer obtained, for example, by performing a thermal oxidation on the surface layer of the silicon substrate 10. A polysilicon layer 12 constitutes the gate electrode of the memory cell unit. The surface of the polysilicon layer 12 is thermally oxidized or silicon oxide is deposited, to provide a silicon oxide layer 13 thereon. Sidewall spacers 14 may be formed on the sidewalls of the memory cell unit gate structure, including the gate dielectric layer 11, the polysilicon gate electrode 12, and the silicon oxide layer 13. Lightly-doped regions 15 and heavily-doped regions 16 are formed in the substrate 10 at designated locations, wherein each of the heavily-doped regions is formed inside its respective lightly-doped counterpart. Each pair of a lightly-doped region and a heavily-doped region constitutes a source/drain region for a memory cell transistor.
After the formation of the basic construction for the memory cell unit is concluded in the substrate 10, as shown in FIG. 1A, a silicon oxide layer 17 is deposited over the entire surface of the substrate, followed by the application of a layer of photoresist 100 by a spin coating procedure. Photolithography is then performed to define a designated pattern in the photoresist layer, so that an opening 110 reveals the surface of the silicon oxide layer 17. Afterwards, as shown in FIG. 1B, the photoresist layer 100 is utilized as a shielding mask during a dry etching procedure, whereby the silicon oxide layer 17 exposed inside the opening 110 of the photoresist layer 100 is consumed, leaving residual portions of the oxide on the sidewalls of the memory cell gate structure. This forms second sidewall spacers 18 for the gate structure, over the previously formed first sidewall spacers 14. The etching is controlled to consume the silicon oxide layer 17 until the surface of the heavily-doped region 16 in the opening 110, between two consecutive gate structures of the memory cell, is revealed. Then, the photoresist layer 100 may be removed. At this stage, another polysilicon layer is deposited over the entire surface of the substrate. The deposited polysilicon layer directly contacts the heavily-doped region 16, which is exposed in the opening 110. As is seen in FIG. 1C, this deposited second polysilicon layer may then be patterned using photolithography and etching to form a configuration as shown in the drawing. This configuration constitutes a contact 19 for the memory cell, and is used as the bit line contact for the memory cell array of the device being fabricated.
Since the thickness of the deposited silicon layer 17 determines the width of the second sidewall spacer 18, therefore, the larger is the thickness of the deposited silicon layer 17, the larger the width of the sidewall spacer 18 will be, and the reverse is also true. When the factor of electrical insulation between contact 19 and gate electrode 12 is considered, it can be understood that the larger the thickness of the deposited polysilicon layer 17 is, the more effective the insulation will be. In addition, the parasitic capacitance will also be smaller. However, a thick polysilicon layer 17 would result in a large gradient discrepancy in the vertical direction for the configuration of the sidewall spacers. This increases the aspect ratio for the subsequent metallization steps of the device fabrication, and increases the level of difficulty in performing metal sputtering. The subsequent planarization would also be worse.